In recent years, with development of large multi-core computing systems such as multi-core Graphic Processing Units (GPUs), demands for high-density and high-performance on-chip caches are increasing. Because of a relatively high leakage current and a relatively low integration degree, conventional caching structures based on a static random access memory (SRAM) have become a bottleneck limiting development of high-performance processing systems. In contrast, a new-type nonvolatile memory (NVM), that stores data by using component resistance changes, can, theoretically, achieve a higher integration degree and an extremely low leakage current, and therefore is deemed as an ideal device for substituting conventional SRAMs.
However, if the NVM is directly used as a caching device, problems of write power consumption, write latency, and write endurance may occur, which limit applications of the NVM in high-speed caches. A nonvolatile SRAM is a memory structure that includes both a SRAM and an NVM. It uses the SRAM to store data in a working mode, and can back up data to the NVM at a power outage. However, after a power outage, the nonvolatile SRAM needs a relatively large on-chip energy storage capacitor to supply power for backing up data, and this kind of capacitors may require relatively high chip area overheads and cost overheads. In addition, as the storage capacity increases, by a high peak current may be generated in a parallel backup process, which reduces system stability. On the other hand, a backup time in a serial backup increases as the backup data volume grows, affecting system performance and causing relatively high data redundancy in the backup process.
An existing backup method using a segment-based parallel compression (SPaC) architecture, is shown in FIG. 1. Data in a SRAM is divided into multiple segments, then a compression module compresses each segment of data by means of run-length encoding, and then compressed data is stored into an NVM unit. In this compression backup method, all data in the SRAM is compressed, and therefore there is a relatively high degree of data redundancy. In addition, when this method is used, compression and decompression operations are required respectively before data backup and before data recovery. Therefore, as a data volume grows larger, a longer compression and decompression time is needed, which affects system performance.